The present invention relates to a wire bonding apparatus, record medium storing bonding control program, and bonding method for detecting non-bonding at a bonding point.
One of the assembly processes for semiconductors such as ICs (integrated circuits) is a wire bonding process for connecting between the semiconductor chip and lead frame with wires.
In a typical wire bonding process, as seen from FIG. 14, pads 3 (first bonding points) of a semiconductor chip 2 and leads 4 (second bonding points) of a lead frame 15, both on a work 14, are connected by wires 12. FIG. 13 shows bonding steps in the conventional wire bonding process, and this conventional wire bonding process will be described below with reference to FIG. 13.
A conventional wire bonding apparatus executes wire bonding by the actions (steps) shown in FIG. 13.                (1) The tip end of a wire 12 is formed into a ball 5, and a capillary 16 is moved over a pad 3 (first bonding point) (step (a)).        (2) The capillary 16 is caused to descend, and bonding is performed on the pad 3 (first bonding point) (step (b)). The ball 5 is pressure-bonded on the pad 3 (first bonding point), so that a first bond portion 6 (pressure-bonded ball) is formed.        (3) After bonding, the capillary 16 ascends, separating from the pad 3 (first bonding point), and then moves laterally (step (c)).        (4) During this lateral movement of the capillary 16, an electric current is made to flow from the wire 12 to the work 14. When, at that time, bonding to the pad 3 (first bonding point) is successful and the bonding has been performed well, an electric current is made to flow from the wire 12 to the work 14 in step (c) (for example Patent Publication 1).        (5) After bonding to the pad 3 (first bonding point), the capillary 16 is moved to the lead 4 (second bonding point), and bonding is performed at the lead 4 (second bonding point).        (6) After bonding to the second bonding point, when the capillary 16 is caused to ascend, an electric current is caused to flow from the wire 12 to the work 14. When bonding to the lead 4 (second bonding point) is successful, and a tail wire 8 is formed properly at the tip of the capillary 16, a current is able to flow from the wire 12 to the work 14. Conversely, if the wire 12 is cut while the capillary 16 is ascending, the current will cease to flow from the wire 12 to the work 14. As a result, it is possible to detect whether or not there is a no-tail with the tail wire 8 not attaining a prescribed length (steps (d) and (e)).        (7) After the bonding to the lead 4 (second bonding point), a clamper 17 closes and ascends together with the capillary 16, and, as a result, the wire 12 is cut above the second bond portion 7 (steps (e) and (f)). After this wire cutting also, a current is made to flow from the wire 12 to the work 14, and non-bonding detection is conducted.        (8) When bonding to the lead 4 (second bonding point) finishes, the capillary 16 is moved toward the next pad 3 (first bonding point).        
In the conventional wire bonding process as described above, wire non-bonding is detected by causing an electric current to flow from the wire 12 to the work 14. This electrical non-bonding detection is executed by devices such as those shown in FIG. 11 and FIG. 12. FIG. 11 shows a direct current (DC) electrical conduction state acquisition device 22a for applying a direct current from a wire to a work, while FIG. 12 shows an alternating current (AC) electrical conduction state acquisition device 22b for causing alternating current to flow from a wire to a work.
The DC electrical conduction state acquisition device 22a, when a wire is connected to a semiconductor chip 2, uses the flow of electric current from the wire 12 to the work 14 to acquire the electrical conduction state for detecting bonding and non-bonding, and it comprises a positive voltage power supply 55 for applying a positive voltage to the wire 12 and a negative voltage power supply 56 for applying a negative voltage to the wire 12. By a switch 54 for switching between those two power supplies, the positive or negative power supply is connected through a resistor 57 to the input side of a detector 58. On the input side of the detector 58, an on-off switch 52 for turning the current to the wire 12 on and off is provided. The on-off switch 52 is connected to the spool 11 on which the wire 12 is wound and thereby electrically connected to the wire 12. The reason why the DC electrical conduction state acquisition device 22a has two types of power supply, namely a positive and a negative one, is that there are circuits on the semiconductor chip 2 which apply a positive current to the pad 3 and circuits which apply a negative current thereto, depending on the circuit configuration.
The DC electrical conduction state acquisition device 22a structured described above acquires the electrical conduction state in the following manner: depending on the properties of the first bonding point, either a positive voltage or a negative voltage power supply is selected by the switch 54; when the on-off switch 52 is closed, because one of the power supplies will be grounded together with the work 14, a current will flow from the power supply 55 or 56 through the pad 3 to the semiconductor chip 2; at that time, when the wire 12 is non-bonding (or is not bonded), then the current will not flow to the wire 12, but will flow toward the detector 58, and the voltage on an output terminal 59 of the detector 58 will either rise or fall (see cf. Patent Publication. H2 (1990)-298874 1 and No. H7 (1995)-94545, for example). This voltage change is sensed and non-bonding is detected accordingly.
Meanwhile, due to the characteristics of the circuitry on the semiconductor chip 2, some pads 3 (first bonding points) have a very large resistance and are not conductive with the work 14, exhibiting characteristics such that a direct current will not flow at all. For such pads 3 (first bonding points) in which a direct current does not flow, the electrical conduction state cannot be detected with the DC electrical conduction state acquisition device 22a described above. For this reason, as a means for acquiring the electrical conduction state of a pad 3 (first bonding point) in which such a DC electrical conduction state acquisition device 22a cannot be used, there are AC electrical conduction state acquisition device 22b. The AC electrical conduction state acquisition device 22b causes an alternating current to flow from the wire 12 to the work 14, making use of the fact that an alternating current will flow due to the electrostatic capacitance of the pad 3 and semiconductor chip 2. The function thereof is similar to that of DC electrical conduction state acquisition device 22a; in other words, an alternating current is made to flow to the wire 12 when the on-off switch 52 is turned on and the electrical conduction state is acquired.
However, with such an AC electrical conduction state acquisition device 22b, in cases where the electrostatic capacitance of pads 3 and semiconductor chips 2 is very small, no alternating current will flow and the electrical conduction state is unable to be detected. In view of the fact that it is difficult to switch between such AC and DC type electrical conduction state acquisition devices 22a and 22b, for one semiconductor chip 2, either a DC type or an AC type is used. For this reason, in one semiconductor chip 2, there are predetermined bonding points on which the electrical conduction state is unable to acquire by the electrical conduction state acquisition device, and non-bonding detection cannot be done using an electrical non-bonding detection step. Such predetermined bonding points are determined by the characteristics of the semiconductor chip 2; as a result, which points are predetermined bonding points is known before bonding, so that the predetermined bonding points, even when no conductivity is detected, are treated as bonded points and not as non-bonded points. After manufacture of semiconductor chips is finished, bonded lead frames are, at random times or after certain time intervals, picked up and tested in a separate testing process using a microscope or the like. However, because such testing is done off-line, the problems is that the results of the tests are not immediately fed back to the operation of the manufacturing apparatus, and defective products are produced in large quantities (see Japanese Patent No. 2992427, for example).
So as to deal with such problems, it has been proposed that products be tested for non-bonding by optical non-bonding detection that is done without taking them off the line (see Japanese Patent No. 2992427 and Patent Publication. H2 (1990)-12932, for example). This process images the bonded portions, and executes non-bonding detection by analyzing the resulting image data. One example of an image in the imaging device visual field 60 thereof is shown in FIGS. 10A and 10B. FIG. 10A shows an image of a normal bond, and FIG. 10B shows a non-bonding condition. At the center of FIG. 10B is a bonding point where there is no pressure-bonded ball; and in the top and below thereof, the bonding positions are shifted. The optical non-bonding detection thus detects non-bonding by detecting the presence or absence of a first bond portion 6 (pressure-bonded ball), or the position thereof, on the image data.
In this conventional method, however, though optical non-bonding detection is done without removing the lead frame from the wire bonding apparatus after bonding, the testing process is a separate process from the bonding process as shown in the flowchart in FIG. 9, and optical testing is conducted, sequentially fetching images of all of the pads 3 after first bonding all of the pads 3 (see Japanese Patent No. 2992427 and Patent Publication No. H2 (1990)-2932, for example).
In such a conventional optical non-bonding testing process as described above, time is required for the testing process because all of the bond portions are optically tested; as a result, the problem is that production efficiency deteriorates. There is also a problem in that overlap wiring such as multilayer interconnections and stack interconnections, which have been more often used due to the increased complexity and higher integration in recent semiconductor chips, cannot be dealt with.
In multilayer interconnections, as shown in FIGS. 6A and 6B, a plurality of rows of pads 3 and 3′ are arranged on the semiconductor chip 2, and a plurality of rows of leads 7 and 7′ are arranged in correspondence therewith. The pad 3 and lead 7 near the end surface of each of the semiconductor chips 2 are connected by wires 12, while the pad 3′ and lead 7′ on the far side from the end surface of the semiconductor chips 2 are connected by wires 12′. This wire 12′, as shown in FIG. 6B, connects the pad 3′ and lead 7′ in such manner that it crosses over the pad 3, lead 7, and wire 12.
On the other hand, as seen from FIGS. 7A and 7B, in stack interconnections, the semiconductor chip 2 has a stratified structure with a plurality of levels, pads 3 are deployed on each of the strata; and, as in the multilayer interconnections described above, the pad 3 and lead 7 near the end surface of the semiconductor chip 2 are connected by wire 12, while the pad 3′ and lead 7′ on the far side from the end surface of the semiconductor chips 2 are connected by wire 12′ in such manner that it crosses over the pad 3, lead 7, and wire 12.
When wire-bonding is performed for such multilayer interconnections or stack interconnections, first the wire 12 near the end surface of the semiconductor chip 2 is bonded, and then the wire 12′ on the far side from the end surface of the semiconductor chip 2 is bonded. However, in view of the fact that the wire 12′ on the far side from the end surface of the semiconductor chip 2 crosses over the pad 3, lead 7, and wire 12 that is near the end surface of the semiconductor chip 2, in optical non-bonding detection that uses an imaging device after bonding is finished, the pad 3 and lead 7 near the end surface of the semiconductor chip 2 hide below the wire 12′ that is on the far side from the end surface of the semiconductor chip 2 cannot be imaged. As a result, non-bonding detection is very difficult to execute.
Furthermore, in the conventional art, since the plan images are processed for optically detecting non-bonding, there is a problem in that, while the first bond portion 6 overlays the pad 3 and can be seen when viewed from above (in a plan), as shown in FIG. 8, in actuality, non-bonding in which the first bond portion 6 is separated from the pad 3 is unable to be detected.